The present invention relates to a method of manufacturing a transistor representated by a thin-film transistor (TFT) formed as a switching element on a glass substrate for use in a liquid crystal display or the like and, more particularly, to a transistor for a liquid crystal display.
A liquid crystal display has been used widely and suitably for image display in a notebook personal computer, a mobile terminal, or the like because of a lower profile and lower power consumption easily achieved therein. In a liquid-crystal display as mentioned above, each pixel is driven by a thin-film transistor (switching).
For the achievement of improved brightness based on an increased aperture ratio and miniaturized pixels (reduced in size and increased in precision), attempts have been made in recent years to reduce the size of the thin-film transistor. However, mere miniaturization (scaling down and necessary adjustments) of a conventional structure may cause adverse effects including large off current, a short-channel effect and a hot-carrier effect.
To prevent the adverse effects, an LDD (Lightly Doped Drain) structure has been used in the TFT as well as in an LSI.
A description will be given to a conventional method of manufacturing a TFT with an LDD structure with reference to FIGS. 1, which are cross-sectional views illustrating the manufacturing process (impurity implantation and the resulting impurity distribution in a semiconductor).
First, a semiconductor layer 2 with a thickness of 10 to 100 nm is formed selectively on a predetermined portion of a glass substrate 1 in accordance with an arrangement pattern for a specific application. There has been a recent approach to using polysilicon (poly-Si: polycrystalline silicon) in the semiconductor layer as a replacement for amorphous silicon (a-Si) that has been used conventionally. According to the approach, a poly-Si layer is formed from an a-Si layer which has been formed on a glass substrate, sequentially subjected to exposure to an excimer laser, and recrystallization (annealing).
Thereafter, a gate insulating layer 3 composed of, e.g., SiO.sub.2 is formed to a thickness of 50 to 100 nm on the glass substrate 1 formed with the semiconductor layer 2 in accordance with the same pattern, followed by a gate electrode 4 further formed on the gate insulating layer 3. At this stage, first impurity ions 5 (serving as donors or acceptors) are implanted by using the gate electrode 4 as a mask.
Specifically, P (phosphorus) ions are implanted with an acceleration voltage of 50 to 80 kV by using 5 to 20% PH.sub.3 diluted with hydrogen (containing 5 to 20% PH.sub.3 in volume) as a source gas to form low-concentration n.sup.- regions 7 in each of which P is at a concentration of 10.sup.15 to 10.sup.18 cm.sup.-3. The process is illustrated in FIG. 1(a) (PH.sub.3.sup.+ is shown as the ions 5 in the drawing).
Although the upper portion of the gate electrode 4 is also doped with phosphorus for obvious reasons, the drawing thereof is omitted here.
Next, a patterned SiO.sub.2 insulating film 6 is formed around the side faces of the gate electrode 4. The patterned insulating film may be formed from a SiO.sub.2 film formed over the entire surface of the substrate 1 and subjected to dry etching or, alternatively, formed through the anodic oxidation of the side faces of the gate electrode 4.
At this state, the second impurity ions 5 are implanted into the semiconductor layer 2.
Specifically, P (phosphorus) ions are implanted with an acceleration voltage of 50 to 80 kV by using 5 to 20% PH.sub.3 diluted with hydrogen as a source gas to form high-concentration n.sup.+ regions 8 in each of which P is at a concentration of 10.sup.19 to 10.sup.21 cm.sup.-3.
By the foregoing process, the semiconductor layer 2 is formed with the LDD regions 7 at a lower impurity concentration and with the source/drain regions 8 at an impurity concentration higher than that of the LDD regions as shown in FIG. 1(b) (PH.sub.3.sup.+ is also shown as the ions 5 in the drawing).
Finally, thermal treatment is performed at, e.g., 850 to 900.degree. C. in a Si MOS transistor for use in an LSI or the like, thereby activating the impurity implanted in the two process steps described above.
In the case of manufacturing a thin-film transistor using a glass substrate or the like, however, it is difficult to perform thermal treatment at a high temperature so that thermal treatment, lamp heating, laser annealing, or the like is normally performed at a temperature on the order of 400 to 600.degree. C.
The thermal treatment thus performed causes the implanted impurity to be bonded to Si, which activates and diffuses the implanted impurity. Consequently, the LDD regions 8 are expanded from the regions immediately under the side faces of the gate electrode 4 to regions closer to the center of the gate electrode.
However, the two steps of impurity implantation should be performed inevitably to form the aforesaid conventional thin-film transistor with the LDD structure, which leads to an increased number of process steps, higher cost, and a degraded production yield.
Although phosphorus is shown in FIGS. 1 by way of example, the number of process steps is preferably minimized in the case of implanting a deadly toxic impurity, such as As, instead.